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| DATA SHEET MOS INTEGRATED CIRCUIT PD63310 STEREO SOUND CODEC The PD63310 is an LSI that features two channels each of on-chip 16-bit ADC and DAC circuits for mutual conversion between digital signals and audio signals (having a maximum signal bandwidth of 24 kHz). The analog signal input block enables mixed input of four different stereo signals and one monaural signal, and the volume of each signal can be controlled before mixing. The PD63310 also features two on-chip microphone amplifiers (mic amps) and gain is adjustable between 10 and 30 dB. The analog signal output block enables mixed output of analog signals output by the DAC and four different stereo analog signals, and the volume of each signal can be controlled before mixing. The digital audio signal I/O block supports a serial interface for audio applications (two's complement, MSB first). A 6-bit parallel port are used for the various volume settings, with volume settings selectable (in 1.5-dB steps) from - 46.5 dB to 0 dB, as well as a mute setting. FEATURES * Two channels each of type ADC and DAC * On-chip mixing circuit in analog I/O block * Low-noise mic amps for two channels on chip * On-chip reference voltage power supply (1.4 V TYP.) * ADC and DAC digital filter characteristics Pass band ripple : 0.1 dB (0 to 0.454 fs) for ADC and DAC Stop band attenuation : 75 dB (0.546 fs or above) for ADC and DAC * Sampling frequency (fs): 2 to 48 kHz (256-fs master clock is input from an external source) * Low voltage operation: +3 to +5.5 V single power supply * Wide operating ambient temperature: -20 to +80C * Low power consumption: 120 mW (when using 3-V power supply), 250 mW (when using 5-V power supply) * 80-pin plastic TQFP RECOMMENDED USES * Speech recognition system, including car navigation system * PC sound system ORDERING INFORMATION Part Number Package 80-pin plastic TQFP (FINE PITCH) (12 x 12 mm) PD63310GK-9EU The information in this document is subject to change without notice. Document No. S11319EJ7V0DS00 (7th edition) Date Published October 1998 N CP(K) Printed in Japan The mark shows major revised points. (c) 1996 PD63310 BLOCK DIAGRAM Digital I/O terminals 2 6 2 I/O interface Digital filter Decimeter Decimeter Interpolator OEB, RBW RB, WB DATA5DATA0 LRCLK MCLK BCLK SELR CSB SO SI Interpolator Analog loopback (for test mode selection) ADC ADC DAC DAC Mixer Mixer Filter Filter MIC AMP MIC AMP Mixer Mixer + - + - MICOL MICPL MICNL IN1L IN2L IN3L IN4L IN5 IN1R IN2R IN3R IN4R MICPR MICNR MICOR OUTL DACL OUTR Analog I/O terminals 2 DACR PD63310 PIN CONFIGURATION (Top View) 80-pin plastic TQFP (FINE PITCH) (12 x 12 mm) * PD63310GK-9EU AGND1 AGND2 AGND3 MICOR MICNR MICPR VRRO VXRO VRLO VXLO VRRI VXRI VRLI VXLI NC NC NC NC NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 IN1R IN2R IN3R IN4R IN5 IN4L IN3L IN2L IN1L NC NC NC NC NC NC MICOL MICNL MICPL RBW OEB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AVDD AGND4 AGND5 OUTL DACL OUTR DACR NC NC NC NC NC DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DGND2 DGND1 WB CSB TEST1 TEST2 RSTB MCLK LRCLK BCLK SELR SO NC NC RB NC SI NC NC NC DVDD NC NC 3 PD63310 PIN FUNCTIONS (1/3) Pin Number 1 2 3 4 5 6 7 8 9 10-15 16 17 18 19 Pin Name IN1R IN2R IN3R IN4R IN5 IN4L IN3L IN2L IN1L NC MICOL MICNL MICPL RBW I/O I I I I I I I I I -- O I I O Function R-channel analog audio signal input pin 1 R-channel analog audio signal input pin 2 R-channel analog audio signal input pin 3 R-channel analog audio signal input pin 4 Analog audio signal (monaural) input pin. This channel accepts audio input which is input to both left and right channels on the chip. L-channel analog audio signal input pin 4 L-channel analog audio signal input pin 3 L-channel analog audio signal input pin 2 L-channel analog audio signal input pin 1 No connection L-channel mic amp output pin. If the L-channel mic amp is not being used, connect this pin to MICNL pin. L-channel mic amp inverting input pin. If the L-channel mic amp is not being used, connect this pin to MICOL pin. L-channel mic amp noninverting input pin. If the L-channel mic amp is not being used, connect this pin to VXLO pin. Output pin for signal that specifies the bus driver's direction. Output is at high level when DATA5 to DATA0 are input pins and is at low level when DATA5 to DATA0 are output pins. If not used, leave unconnected. Bus driver enable signal output pin. When data input to DATA5 to DATA0 is enabled, output is at low level. If not used, leave unconnected. No connection Input pin for parallel interface's data write signal. Used for input of low-level signals when addresses are written to the volume setting register and when data is written. Input pin for parallel interface's data read signal. Used for input of low-level signals when data is read from the volume setting register. Input pin for parallel interface's chip select signal. Active low. When the input signal is at high level, DATA5 to DATA0 are set for high impedance. Input pin for signal that specifies the target register for parallel data input and output. Specifies an address register when the input signal is at low level, or a data register when the input signal is at high level. Test mode setting pins. These pins set the test mode when at high level. When not used (i.e., during normal operation mode), connect these pins to GND. Reset signal input pin. A reset occurs when a low pulse (pulse width of 1/ (8 fs) or greater) is input after starting MCLK. The case when a reset is necessary is not only power-on but also an occurrence of disturbance in master clock due to changing fS (sampling frequency). When input is at low level, power down mode is set to reduce power consumption. No connection 20 21, 22 23 OEB NC WB O -- I 24 25 26 RB CSB SELR I I I 27, 28 TEST1, TEST2 I 29 RSTB I 30 NC -- 4 PD63310 (2/3) Pin Number 31 32 Pin Name MCLK LRCLK I/O I O Function Master clock input pin. Used for input of 256-fs clock (duty: 40 to 60%). Serial interface's frame sync clock output pin. Used for L channel data I/O when LRCLK = low level Used for R channel data I/O when LRCLK = high level 33 BCLK O Serial interface's bit sync clock output pin. Used for I/O of audio data from SI and SO in sync with BCLK. BCLK is generated on-chip as MCLK divided by eight. Serial interface's data input pin. Used for serial input (synchronized with BCLK) of audio data (two's complement, MSB first). No connection Serial interface's data output pin. Used for serial output (synchronized with BCLK) of audio data (two's complement, MSB first). Digital power supply pin. Used for input voltage range of +3 to +5.5 V. No connection Digital ground pins. Parallel data I/O pins. Used for input/output of address data and volume setting data. No connection R-channel DAC output pin. When this pin is used, the R-channel DAC output can be monitored without attenuation regardless of the volume setting. R-channel analog audio output pin. L-channel DAC output pin. When this pin is used, the L-channel DAC output can be monitored without attenuation regardless of the volume setting. L-channel analog audio output pin. Analog ground pins. Analog power supply pin. Used for input voltage range of +3 to +5.5 V. No connection Reference voltage input pin for R-channel DAC. This pin is usually connected to VRRO pin. Reference voltage output pin for R-channel DAC. Output is 1.4 V (TYP.). Connects to analog GND via a bypass capacitor. Reference voltage input pin for L-channel DAC. This pin is usually connected to VRLO pin. Reference voltage output pin for L-channel DAC. Output is 1.4 V (TYP.). Connects to analog GND via a bypass capacitor. Reference voltage input pin for R-channel ADC. This pin is usually connected to VXRO pin. Reference voltage output pin for R-channel ADC. Output is 1.4 V (TYP.). Connects to analog GND via a bypass capacitor. Reference voltage input pin for L-channel ADC. This pin is usually connected to VXLO pin. No connection 34 35 36 37 38-40 41, 42 43-48 49-53 54 55 56 57 58, 59 60 61, 62 63 64 65 66 67 68 69 70 SI NC SO DVDD NC DGND1, DGND2 DATA5-DATA0 NC DACR OUTR DACL OUTL AGND5, AGND4 AVDD NC VRRI VRRO VRLI VRLO VXRI VXRO VXLI NC I -- O -- -- G I/O -- O O O O G -- -- I O I O I O I -- 5 PD63310 (3/3) Pin Number 71 72 73 74, 75 76 77 78 79, 80 Pin Name VXLO AGND3 NC AGND2, AGND1 MICPR MICNR MICOR NC I/O O G -- G I I O -- Function Reference voltage output pin for L-channel ADC. Output is 1.4 V (TYP.). Connects to analog GND via a bypass capacitor. Analog ground pin. No connection Analog ground pins. R-channel mic amp noninverting input pin. If the R-channel mic amp is not being used, connect this pin to VXRO pin. R-channel mic amp inverting input pin. If the R-channel mic amp is not being used, connect this pin to MICOR pin. R-channel mic amp output pin. If the R-channel mic amp is not being used, connect this pin to MICNR pin. No connection 6 PD63310 1. DESCRIPTION OF OPERATIONS 1.1 Analog Input Block The analog input block enables signal input from two channels. Four different stereo signals (IN1 to IN4) and a monaural signal (IN5) can be mixed and input via these channels. The volume can be adjusted for each analog signal, and the sum of the volume settings is input to the ADC. A 6-bit signal is used to adjust the volume within an adjustment range (in 1.5-dB steps) from -46.5 dB to 0 dB, plus a mute setting. A low-noise mic amp (variable gain width: 10 to 30 dB) is provided on-chip for mic input. 1.2 Analog Output Block The analog output block enables signal output from two channels. Five different analog signals (IN1 to IN4 and DAC) can be mixed and output via these channels. The volume can be adjusted for each analog signal, and the sum of the volume settings is output (via OUTL and OUTR pins). A 6-bit signal is used to adjust the volume within an adjustment range (in 1.5-dB steps) from -46.5 dB to 0 dB, plus a mute setting. The output from the DAC (via DACL and DACR pins) can be monitored directly. 1.3 Digital Interface A serial interface for audio is supported for input and output of digital audio data (two's complement, MSB first). BCLK and LRCLK are automatically generated on chip from the master clock that is supplied to MCLK pin from an external source. BCLK and LRCLK are used by the ADC and DAC. In other words, the ADC's and DAC's sampling frequency is determined based on the master clock and cannot be set independently of it. A parallel interface is used for input and output of the 6-bit data used for volume adjustments. The target registers for parallel data I/O are selected via the SELR pin. This pin selects an address register when at low level and a data register when at high level. OEB is output as the bus driver's enable signal and RBW is output as the bus driver's direction specification signal. Use this pin as necessary. If it is not used, leave it unconnected. When the clock (data) input to the MCLK and SI pins has been stopped, set these pins to either high level or low level (if necessary, connect via a resistance to DVDD or DGND). (1) Serial interface BCLK LRCLK L-channel data SI, SO 15 14 13 12 4 3 2 1 0 LSB 15 14 13 12 R-channel data 4 3 2 1 0 LSB (2) Parallel interface CSB RB WB OEB RBW (I) (I) (I) (O) (O) DATA5- (I/O) DATA0 7 PD63310 1.4 Volume Setting Register Addresses After the power is turned on and a reset has been input, all volume settings are set to mute mode. Therefore, it may be necessary to specify volume settings before inputting signals. Write data to the volume setting registers that correspond to the analog input pins and analog output pins to be used. Since the ADC's full scale analog input signal amplitude voltage is 1.4 V (TYP.), it may be necessary to specify a volume setting whereby the signal amplitude's maximum voltage (after mixing) is no more than 1.4 V, especially when several analog signals are input to the ADC after mixing. The addresses of the various volume setting registers are specified via the 6-bit parallel data that is input from the DATA5 to DATA0 pins during low-level input to the SELR pin. The volume setting registers corresponding to these addresses are listed below. 0 1 2 3 4 5 6 7 8 9 : IN1L control register : IN1R control register : IN2L control register : IN2R control register : IN3L control register : IN3R control register : IN4L control register : IN4R control register : IN5 control register : IN1L-OUTL control register 10 : IN1R-OUTR control register 11 : IN2L-OUTL control register 12 : IN2R-OUTR control register 13 : IN3L-OUTL control register 14 : IN3R-OUTR control register 15 : IN4L-OUTL control register 16 : IN4R-OUTR control register 17 : DACL-OUTL control register 18 : DACR-OUTR control register 8 PD63310 1.5 Volume Setting Register Data (Command Types) The data in the volume setting registers is written and read based on 6-bit parallel data that is input and output via the DATA5 to DATA0 pins when the SELR pin is set for high level input. The data (commands) in the various volume setting registers are described below. 0: D5 D4 D3 D2 D1 D0 D4 to D0 indicate the data used to control gain in the IN1L register's input signal, with codes corresponding to the gain levels listed in Table 1-1 below. When D5 is "1", mute mode is set. Table 1-1. Correspondence of Codes and Gain Levels D5 0 0 0 | 0 0 1 1 D4 0 0 0 | 1 1 0 x D3 0 0 0 | 1 1 0 x D2 0 0 0 | 1 1 0 x D1 0 0 1 | 1 1 0 x D0 0 1 0 | 0 1 0 x Gain 0 dB -1.5 dB -3.0 dB | -45.0 dB -46.5 dB MUTE Note MUTE Note Default value Remark x : Don't care 1: D5 D4 D3 D2 D1 D0 D4 to D0 indicate the data used to control gain in the IN1R register's input signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 2: D5 D4 D3 D2 D1 D0 D4 to D0 indicate the data used to control gain in the IN2L register's input signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 3: D5 D4 D3 D2 D1 D0 D4 to D0 indicate the data used to control gain in the IN2R register's input signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 4: D5 D4 D3 D2 D1 D0 D4 to D0 indicate the data used to control gain in the IN3L register's input signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 5: D5 D4 D3 D2 D1 D0 D4 to D0 indicate the data used to control gain in the IN3R register's input signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 6: D5 D4 D3 D2 D1 D0 D4 to D0 indicate the data used to control gain in the IN4L register's input signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 9 PD63310 7: D5 D4 D3 D2 D1 D0 D4 to D0 indicate the data used to control gain in the IN4R register's input signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 8: D5 D4 D3 D2 D1 D0 D4 to D0 indicate the data used to control gain in the IN5 register's input signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 9: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when mixing the IN1L register's input signal with the L-channel DAC's output signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 10: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when mixing the IN1R register's input signal with the R-channel DAC's output signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 11: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when mixing the IN2L register's input signal with the L-channel DAC's output signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 12: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when mixing the IN2R register's input signal with the R-channel DAC's output signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 13: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when mixing the IN3L register's input signal with the L-channel DAC's output signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 14: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when mixing the IN3R register's input signal with the R-channel DAC's output signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 15: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when mixing the IN4L register's input signal with the L-channel DAC's output signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 16: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when mixing the IN4R register's input signal with the R-channel DAC's output signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 10 PD63310 17: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when outputting the L-channel DAC's output signal to OUTL, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 18: D5 D4 D3 D2 D1 D0 D4 to D0 indicate data that controls the gain when outputting the R-channel DAC's output signal to OUTR, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1. 1.6 Test Mode Test mode is set (and MCLK input is required) when the TEST1 and TEST2 pins are at high level. When in test mode, the IC internally inputs the ADC's output directly to the DAC (via an analog loopback). This analog loopback enables verification of analog circuit operations and the volume settings. 11 PD63310 2. SYSTEM CONNECTIONS 2.1 Analog Input Block A frequency that is one half of the master clock (MCLK) frequency is used as the ADC's and DAC's oversampling frequency. Accordingly, if there is no input of high-frequency noise that is close to MCLK/2 (= 128 fs), the filter (LPF) inserted before the analog block can be omitted (see Figure 2-1). The analog signal input pins (pins 1 to 9) are internally biased to 1.4 V (TYP.), so a coupling capacitor (1 to 4.7 F) should be inserted. The full scale analog input signal level is 1.4 Vp-p (TYP.). Adjust the transmitting side's level so that the amplitude of the signal that is input to an analog audio signal input pin does not exceed 1.4 Vp-p. In particular, if this signal's amplitude exceeds 2.8 Vp-p, the analog signal input pin's voltage may become less than 0 V during negative amplitude, which may prevent the volume control from operating normally (such as when there is signal leakage during mute mode). Analog signal input pins that are not used should be left unconnected or connected to a GND pin via a capacitor. Figure 2-1. Analog Input Block Connection Example (Using IN1R Pin) + 4.7 F IN1R etc. 2.2 Mic Amp The mic amp's gain can be adjusted (between 10 dB (MIN.) and 30 dB (MAX.)) via an external resistor. The gain setting is adjusted by changing R1. R2 is fixed at 100 k (see Figure 2-2). Gain is calculated via the following expression. Mic amp gain calculation: AV = 20 log ((R2 + R1)/R1) [dB] Since the mic amp is independent from other blocks, if the mic amp's output is input to the ADC (or is mixed with output from the DAC), the mic amp's output pin should be connected via a coupling capacitor to one of the analog signal input pins (see Figure 2-1). Separate the unused mic amp from R1 and the electrolytic capacitors (shown in Figure 2-2) and set 0 for R2. Figure 2-2. Mic Amp Connection Example (Using Right Side) To VXRO R2 = 100 k + 4.7 F + 4.7 F R1 = 10 k R1 = 10 k MICNR R2 = 100 k MICOR To analog signal input pins MICPR Remark When the above example is a constant, the mic amp's gain becomes about 21 dB. 12 PD63310 2.3 Analog Output Block The analog audio output pins (OUTL and OUTR) and the DAC output pins (DACL and DACR) are internally biased to 1.4 V (TYP.), so an output coupling capacitor should be inserted to cut the DC component (see Figure 2-3). The out-of-band component of the output signals from these analog pins is attenuated by a post filter (LPF) in the IC, so there is no need for an external LPF. Set the load resistance to at least 20 k (the speakers cannot be directly driven, so insert a power amp IC before the speaker). Analog audio output pins and DAC output pins that are not used can be left unconnected. Figure 2-3. Analog Output Block Connection Example OUTL etc. + 4.7 F 33 k 2.4 Use Cautions When changing the volume (addresses 17 and 18) between the DAC output and the output mixer, noise ("pop noise") may be output from an analog audio output pins (OUTL or OUTR). Such noise is due to the output offset voltage of an on-chip DAC. If this noise is audible enough to be a problem, take the following measures. (1) Set mute mode for the volume (addresses 17 and 18) between the DAC output and the output mixer. (2) Connect the DAC output pins (DACL and DALR) via a capacitor to a pair of unused analog input pins (such as IN4L and IN4R). (3) Adjust the volume (such as addresses 15 and 16) between the analog input pins connected as described in (2) above and the output mixer to adjust the DAC output volume. 13 PD63310 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (unless otherwise specified, DGND = AGND = 0 V) Parameter Power supply voltage Analog input voltage Digital input voltage Applied voltage to analog output pin Applied voltage to digital output pin Operating ambient temperature Storage temperature Symbol VDD VAIN VDIN VAOUT VDOUT TA Tstg All VDD pins All analog input pins All digital input pins All analog output pins All digital output pins Conditions Rating -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -20 to +80 -65 to +150 Unit V V V V V C C Caution If the absolute maximum rating for any of the above parameters is exceeded even momentarily, it may adversely affect the quality of this product. In other words, these absolute maximum ratings have been set to prevent physical damage to the product. Do not use the product in such a way as to exceed any of these ratings. Recommended Operating Conditions (unless otherwise specified, DGND = AGND = 0 V, load capacitance = 20 pF, and on-chip reference voltage power supply is used) Parameter Power supply voltage Operating ambient temperature Master clock frequency Sampling frequency Digital input voltage (high level) Digital input voltage (low level) Digital input voltage (high level) Digital input voltage (low level) RSTB rise time Analog input signal voltage ADC input signal voltage Analog output signal voltage Analog output pin load resistance Mic amp voltage gain Symbol VDD TA fMCLK fs VIH VIL VIH VIL trRSTB VI VIADC VO RL AVMIC When VDD = 5.0 V When VDD = 5.0 V When VDD = 3.3 V When VDD = 3.3 V Time required to change from 10% to 90% of VDD All analog input pins Mixer output section (before ADC) OUTL and OUTR pins (mixer output section) All analog output pins 256 fs All VDD pins Conditions MIN. 3.0 -20 0.512 2 4.5 0 2.64 0 -- -- -- -- 20 10 20 25 TYP. MAX. 5.5 80 12.288 48 5 1.0 3.3 0.66 1 1.4 1.4 1.4 -- 30 Unit V C MHz kHz V V V V s Vp-p Vp-p Vp-p k dB 14 PD63310 DC Characteristics (unless otherwise specified, TA = -20 to +80C, DVDD = AVDD = 3.0 to 5.5 V, DGND = AGND = 0 V) (1) Power consumption Parameter Operating current Operating current Standby current Symbol IDD IDD IDDstb Conditions When VDD = 5.0 V When VDD = 3.0 V Power down mode MIN. -- -- -- TYP. 50 40 1.5 MAX. 70 60 2 Unit mA mA mA (2) Digital block Parameter Input leakage current Output leakage current High-level output current Low-level output current High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Symbol ILI ILO IOH IOL VOH VOL VOH VOL Conditions When VDD = 5.0 V and VI = 5.0 to 0.0 V When VDD = 5.0 V and VO = 5.0 to 0.0 V (high impedance) When VDD = 5.0 V and VO = 4.0 V When VDD = 5.0 V and VO = 0.4 V When VDD = 5.0 V and IO = -2.0 mA When VDD = 5.0 V and IO = 2.0 mA When VDD = 3.3 V and IO = -2.0 mA When VDD = 3.3 V and IO = 2.0 mA MIN. -5.0 -5.0 -2.0 -- 4.0 -- 2.64 -- TYP. MAX. +5.0 +5.0 -- +2.0 -- 0.4 -- 0.4 Unit A A mA mA V V V V (3) Analog block Parameter Reference power supply output voltage, AD side Reference power supply output voltage, DA side Input resistance 1 Input resistance 2 Symbol VXL (R) VRL (R) RI1 RI2 Conditions VXRO and VXLO pins VRRO and VRLO pins IN1L, IN2L, IN3L, IN4L, IN1R, IN2R, IN3R, and IN4R pins IN5 pin MIN. 1.35 1.35 6.5 13 TYP. 1.4 1.4 10 20 MAX. 1.45 1.45 15 30 Unit V V k k 15 PD63310 Transmission Characteristics (unless otherwise specified, TA = -20 to +80C, DVDD = AVDD = 3.0 to 5.5 V, DGND = AGND = 0 V, master clock = 12.288 MHz, and on-chip reference voltage power supply is used) (1) AD side Parameter AD peak S/N AD dynamic range AD idle noise AD absolute gain AD relative gain 1 AD relative gain 2 AD frequency gain characteristic AD total harmonic distortion AD full-scale analog input amplitude AD offset voltage THDX VIFS VOFFX Signal = 1 kHz, 0 dB input Signal = 1 kHz, 0 dB input -- 1.35 -100 -50 1.4 10 -40 1.45 +100 dB Vp-p mV Symbol SNPX SNX ICNX GX GVX1 GVX2 GRX Signal = 1 kHz, 0 dB input -22.5 to -1.5 dB (0-dB reference) -46.5 to -24.0 dB (0-dB reference) 0 to 20 kHz Conditions Signal = 1 kHz, in 0 to 20 kHz bandwidth -60 dB input MIN. 60 60 -- -1.0 -2.0 -5.0 -0.5 TYP. 75 75 -75 0.5 1.0 2.0 0.1 MAX. -- -- -60 +1.0 +2.0 +5.0 +0.5 Unit dB dB dB dB dB dB dB (2) DA side Parameter DA peak S/N DA dynamic range DA idle noise DA absolute gain DA relative gain 1 DA relative gain 2 DA frequency gain characteristic DA total harmonic distortion DA full-scale analog output amplitude DA offset voltage Symbol SNPR SNR ICNR GR GVR1 GVR2 GRR THDR VOFS VOFFR Signal = 1 kHz, 0 dB input -22.5 to -1.5 dB (0-dB reference) -46.5 to -24.0 dB (0-dB reference) 0 to 20 kHz Signal = 1 kHz, 0 dB input Signal = 1 kHz, 0 dB input Conditions Signal = 1 kHz, in 0 to 20 kHz bandwidth -60 dB input MIN. 60 60 -- -1.0 -2.0 -5.0 -0.5 -- 1.35 -100 TYP. 75 75 -75 0.5 1.0 3.0 0.2 -50 1.4 30 MAX. -- -- -60 +1.0 +2.0 +5.0 +0.5 -40 1.45 +100 Unit dB dB dB dB dB dB dB dB Vp-p mV 16 PD63310 AC Characteristics (unless otherwise specified, TA = -20 to +80C, DVDD = AVDD = 3.0 to 5.5 V, DGND = AGND = 0 V) Parameter RSTB-CSB setup time RSTB-SELR setup time CSB-WB setup time SELR-WB setup time SELR-WB hold time Time between SELR and WB WB-CSB hold time WB low-level width RB low-level width Data valid time after WB DATA-WB setup time WB-DATA hold time Time between SELR and RB RB-SELR hold time Data delay time after RB RB-DATA hold time DATA-CSB hold time DATA IN setup time DATA IN hold time DATA OUT setup time DATA OUT hold time Symbol tRSUC tRSUS tCSSUW tSESU tSEHD tBSW tCSHD tSTW tRSTW tWDDV tWDSU tDHDW tBSR tSEHDR tRDDV tDHDR tCSHDR tDIS tDIH tDOD tBLD Conditions MIN. 0 0 0 0 60 0 60 120 200 0 30 30 0 60 0 0 30 100 100 -40 0 TYP. MAX. -- -- -- -- -- -- -- -- -- 90 -- -- -- -- 150 20 -- -- -- +65 45 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17 PD63310 Parallel interface write timing 1 RSTB tRSUC CSB tCSSUW tCSHD SELR tRSUS tSESU tSEHD tBSW WB tSTW DATA5DATA0 tWDDV tWDSU tDHDW tWDDV tWDSU tDHDW OEB RBW 18 PD63310 Parallel interface write timing 2 (when there are continual write cycles while CSB is low) RSTB tRSUC CSB tCSSUW SELR tRSUS tSESU tSEHD tBSW tSEHD tSESU WB tSTW DATA5DATA0 tWDDV tWDSU tDHDW tWDDV tWDSU tDHDW OEB RBW the different part from "Parallel Interface write timing 1" 19 PD63310 Parallel interface read timing 1 RSTB tRSUC CSB tCSSUW tCSHDR SELR tRSUS tSESU tSEHD WB tSTW tBSR RB tRSTW DATA5DATA0 tWDDV tWDSU tDHDW tRDDV tDHDR OEB RBW 20 PD63310 Parallel interface read timing 2 (when there are continual read cycles while CSB is low) RSTB tRSUC CSB tCSSUW SELR tRSUS tSESU tSEHD tSEHDR tSESU WB tSTW tBSR RB tRSTW DATA5DATA0 tWDDV tWDSU tDHDW tRDDV tDHDR OEB RBW the different part from "Parallel Interface read timing 1" 21 PD63310 Serial interface input timing BCLK tDIS tDIH SI Serial interface output timing BCLK tDOD SO tBLD tBLD LRCLK 22 PD63310 4. APPLICATION CIRCUIT EXAMPLE 100 k 4.7 F + 10 k To VXRO 4.7 F + 10 k 100 k + + + + 0.1 Fx4 4.7 Fx4 (tantalum) 0.1 F 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 4.7 F + AGND1 AGND2 AGND3 VXLI VXRI VRLI MICOR MICNR MICPR VXLO VXRO VRLO VRRO VRRI NC NC NC NC R-ch mic input R-ch line input Monaural line input L-ch line input L-ch mic input 4.7 Fx9 + + + + + + + + + 1 IN1R 2 IN2R 3 IN3R 4 IN4R 5 IN5 6 IN4L 7 IN3L 8 IN2L 9 IN1L 10 NC 11 NC 12 NC 13 NC 14 NC NC NC AVDD 60 AGND4 59 AGND5 58 OUTL 57 DACL 56 OUTR 55 DACR 54 NC 53 NC 52 NC 51 NC 50 NC 49 DATA0 48 DATA1 47 DATA2 46 DATA3 45 DATA4 44 DATA5 43 DGND2 42 33 kx4 + + + + 4.7 Fx4 L-ch line output R-ch line output D0 D1 D2 D3 D4 D5 4.7 F 100 k + 10 k + 4.7 F 10 k 100 k To VXLO 15 NC 16 MICOL 17 MICNL 18 MICPL 19 RBW LRCLK TEST1 TEST2 MCLK 20 OEB DGND1 41 RSTB SELR BCLK DVDD CSB WB SO NC NC NC NC NC NC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 + 0.1 F 4.7 F Microcontroller digital I/O Reset Audio digital I/O Remark : Analog ground : Digital ground NC RB SI 6 23 PD63310 5. RECOMMENDED LAYOUT PATTERN When laying out the power supply lines and GND lines on the circuit board, refer to the following figure concerning the layout of bypass capacitors. Figure 5-1. Diagram of Recommended Bypass Capacitor Connections (Top View) + AVDD AGND4 AGND5 + VRRI VRRO + VRLI VRLO + VXRI VXRO + VXLI VXLO AGND3 AGND2 AGND1 SYSTEM ANALOG GND DIGITAL GND DGND2 DGND1 + DVDD Remark + (4.7 F) : Tantalum capacitor (0.1 F) : Chip ceramic capacitor 24 PD63310 6. PACKAGE DRAWING 80 PIN PLASTIC TQFP (FINE PITCH) ( 12) A B 60 61 41 40 detail of lead end C D S 80 F 21 1 20 G H I M J K P N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. M ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.1450.05 0.10 1.00.05 0.10.05 3 +7 -3 1.2 MAX. Q R INCHES 0.5510.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.5510.008 0.049 0.049 0.009+0.002 -0.003 0.004 0.020 (T.P.) 0.039+0.009 -0.008 0.020+0.008 -0.009 0.006 +0.002 -0.003 0.004 0.040 +0.002 -0.003 0.0040.002 3 +7 -3 0.048 MAX. S80GK-50-9EU 25 PD63310 7. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our sales representative. Table 7-1. Soldering Conditions for Surface Mounting Type PD63310GK-9EU: 80-pin plastic TQFP (FINE PITCH) (12 x 12 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (at 210C or higher), Number of reflow processes: 2 max., Exposure limitNote : 7 days (after that, prebaking is necessary at 125C for 10 hours) VPS Package peak temperature: 215C, Reflow time: 40 seconds or below (at 200C or higher), Number of reflow processes: 2 max., Exposure limitNote : 7 days (after that, prebaking is necessary at 125C for 10 hours) Pin partial heating Pin temperature: 300C or below, Time: 3 seconds or below (per device side) -- VP15-107-2 Symbol IR35-107-2 Note The number of days for storage after the dry pack has been opened. Storage conditions are 25C and 65% RH max. Caution Do not use two or more soldering methods in combination (except for pin partial heating method). 26 PD63310 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 27 PD63310 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 |
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